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August 27, 2014

Lithography Challenges for 2.5D Interposer Manufacturing

Presented at ECTC 2014 

In recent years, 2.5D packaging has quickly turned from a buzzword into an Advanced Packaging reality. Not dissimilar to the Multi-Chip-Modules (MCMs) of the past, 2.5D packages utilizing high density interposers with favorable electrical characteristics can be a cost efficient and high performance alternative to significantly more complex 3D or SOC integration schemes.

Dictated by the trend towards ever thinner, smaller and higher integrated and more capable devices, high density interposer technology is required to enable 2.5D packages. Patterning of these kinds of substrates, regardless if manufactured on silicon, glass or other suitable materials requires relatively advanced lithography systems. Simple contact or proximity exposure is no longer up to the task.

This paper specifically lists the various patterning / lithography challenges which are being encountered when manufacturing high density 2.5D interposers. Typical back-end lithography requirements regarding minimum resolution, overlay, maximum sidewall angle capability in relatively thick resist and depth of focus are established and discussed. In addition, the application-specific lithography challenges such as a large exposure field size, IR backside alignment capability for TSV (Through-Silicon-Via) or TSG (Through-Glass-Via) definitions and warped wafer or substrate handling are being reviewed and characterized.

As with all back-end processes, interposer manufacturing must be extremely cost efficient and high yielding. A middle ground between costly front-end processes and more robust, faster and lower cost back-end processes has to be found. This paper also discusses potential cost reduction via economy of scale. A lithography cost analysis for glass interposer manufacturing on large panels is being offered.

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