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September 11, 2013

Controlling Bumping Processes with Picosecond Ultrasonic Metrology

Chip Scale Review, Sept/Oct 2013

Advanced packaging processes continue to follow a development path similar to front-end processes, with increasing process complexity and decreasing feature size demanding greater attention to inspection and metrology to control processes and maintain yields. In addition, the high value of the known good die being packaged multiplies the cost of scrap and the benefit of increasing yield. The adoption of advanced packaging has driven an increase in interconnect density with more I/O connections in smaller form factors. Bumps used in fine-pitch, high-density interconnects are now as small as 15µm diameter at a 40µm pitch. Importantly, the plating processes used to create these bumps and interconnects exhibit pattern dependent variations that require direct measurements on product wafers to ensure adequate process control. 

Bumping processes came into widespread use with the adoption of flip-chip packaging processes. Flip-chip processes generally use solder bumps and can create bumps with pitches down to 150µm. In response to the demand for higher interconnect densities, manufactureres have developed advanced packaging processes that interpose complex structures between the chip(s) and the package to route electrical signals and secure the chip mechanically to the package. 

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