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September 23, 2015

Performance of Optimized Lithography Tools and Materials in Advanced Packaging Applications

Chip Scale Review, Sept/Oct 2015

Recent years have seen rapid development in the area of advanced packaging. In general, advanced packaging processes are concerned with the interconnection of multiple chips in a single package to provide increased functionality and performance in a smaller volume. Often advanced packaging processes are adaptations of front-end processes. Their development is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. A number of technologies are in development or in production including wafer-level chip-scale packaging, copper pillar bumps on through-silicon vias (TSVs), fan-out wafer-level processing (FOWLP), and many more.

One technology that has gained rapid acceptance is 2.5D packaging. Similar to the multi-chip-modules (MCMs) of the past, 2.5D packaging processes use an interposer to route signals between the device die and the package substrate. The interposer is a multilayered “circuit board” fabricated on a silicon substrate and using through-silicon vias to pass signals from multiple die to the package substrate. 2.5D packages using high-density interposers can be a cost-effective, high-performance alternative to significantly more complex 3D or system-on-chip (SoC) integration schemes. Most estimates project growth for 2.5D/interposer packaging faster than the industry as a whole.

A key enabling technology for interposers has been the development of copper pillar bump technology to provide the high-density interconnection between the interposer and the die. Copper pillar bumps provide a number of advantages over the solder bump technology they are supplanting. They can deliver fine pitches down to 50μm in-line and 40/80μm when staggered. They can reduce costs by reducing the number of layers required in the substrate. They provide superior electromigration performance for high-current carrying capacity applications. They permit electrical test at wafer-level prior to copper pillar bump. They are compatible with bond pad opening/pitch and pad metallization of die designed for wire bond, which enables quick time-to-market for conversion to flip chip.

Lithography is a key component of 2.5D integration schemes, however the requirements for interposer exposure systems differ significantly from the requirements of front-end lithography tools. In particular, 2.5D lithography faces specific challenges in regard to resolution, overlay, sidewall angle, exposure field size, depth-of-focus, warped substrate handling and backside alignment.

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