December 1, 2010
Optimizing Test Cell Performance with Probe Card and Probe Mark Analysis
Wafer and Device Packaging Interconnect, November/December 2010
"A recent study found that optimization using probe card analysis and probemark analysis can significantly improve test cell performance.
The ability to optimize the wafer testing process is critical in minimizing yield losses from the testing process and ensuring test capability for shrinking circuits. Integrated circuit (IC)manufacturers test their products after thewafer fabrication process is completed to ensure that the chips are functioning correctly and to sort the chips on the basis of their performance. Testing allows them to avoid the cost of packaging defective chips and to charge premiumprices for chips with higher performance."