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November 25, 2013

Inspection and Metrology Solutions for Copper Pillar High Volume Manufacturing

Presented at IWLPC, November 2013


The Semiconductor industry has been accelerating the adoption of copper pillar bumping. Copper pillar as an interconnect has been used for Flip-Chip Ball Grid Arrays (FC-BGA) for a few years. Fine pitch copper pillar is also considered a key interconnect technology for the emerging TSV applications and several companies have announced it as an interconnect between packages for POP (Package on Package) applications. Rudolph has developed a suite of solutions that incorporate inspection, metrology and software enabling rapid yield ramp. The solution set applies to copper pillar bumping, not just for standard thickness wafer, but also for thinned bonded and warped wafers when copper pillars are the interconnect to Through-Silicon Vias (TSV). Rudolph will discuss an inspection system that incorporates multiple metrology sensors to provide complete 2D and 3D measurement and inspection solutions.

To download the rest of the white paper