July 14, 2015
Fan-out wafer level packaging set to expand
Solid State Technology, July 2015
The expansion of fan-out is finally coming, says Rich Rogoff, Vice President and General Manager, Lithography Systems Group at Rudolph Technologies.
Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.
Strong growth is now expected, hoped in part by the arrival of 2nd generation FOWLP. “Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size”, explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement.
Rudolph’s Rogoff believes it will be implemented in a wafer form for the next year or two, but will ultimately transition to a panel-based approach. “The big question for the industry is are they going to move to panels?” Rogoff asked. “From a lithography perspective, the tools are ready today. As the demand goes up, there will be a push also for a switch,” he said. “Development of panels has already started and will continue to increase in activity over the next year.”
In an article in Solid State Technology published in 2014, titled “A square peg in a round hole: The economics of panel-based lithography for advanced packaging,” Rogoff said moving from round wafers to rectangular panels (“panel-ization”) saves corner space, delivering a roughly 10% improvement in surface utilization. The larger size of the substrate and the improved fit between the mask and substrate reduce the transfer overhead by a factor of 5. The potential reduction in throughput resulting from an increase in the number of alignment points is more than offset by the improvements in throughput. Compared to a 1X stepper on wafers, panel-based processes can reduce lithography cost per die by as much as 40%.