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January 18, 2017

Addressing Advanced Packaging Challenges in 2017 and Beyond

3D InCites, January 2017

As the two-dimensional (2D) shrinking of planar circuits (on which Gordon Moore based his famous observation) has become more difficult and expensive, the semiconductor industry has had to find other ways to continue to put more computing power and speed into less volume. At the same time, consumers are demanding greater functionality that integrates a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required by these increasingly complex systems. Advanced packaging is now an integral part of most scaling and functionality roadmaps.

By incorporating 2.5D, 3D, and wafer level chip scale packaging (WLCSP), both fan-in and fan-out technologies, manufacturers are able to meet consumer demand for miniaturization and increased functionality while reducing costs and improving performance. The common theme across the various packaging technologies is to shrink the re-distribution layer (RDL) line/space (L/S) pitch, which, in turn, requires increased sensitivity in the technologies used to control the manufacturing process.

During the IMAPS conference a few months ago, several speakers identified fan-out WLCSP as a disruptive technology for several reasons:

  • Simplification of the manufacturing process – it eliminates micro bumps, C4 bumps, through silicon via (TSV) and interposers.
  • Improved cost – For WLCSP, the absence of a substrate leads to lower cost. In processes that use substrates, they account for 35 percent of the packaging cost — a significant number.
  • Driving innovation – The technology can be used for multiple dies in package-on-package form as well as side-by-side, reducing the overall form factor required for mobile and the internet of things (IoT) applications. It also allows chip manufacturers to mix devices from advanced process nodes and mature nodes.

The idea is very simple: fab-like processes designed to work on conventional wafers to provide signal routing and I/O on the expanded surface area of the reconstructed wafer.  However, several challenges exist, including kerf chipping and cracking during singulation, warpage, die placement, and non-visual killer defects, to name a few. For this discussion, we will focus on non-visual killer defects.

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